1. Field of the Invention
This invention relates to a variable-ratio frequency divider having a wide range of frequency-dividing ratio and suitable for high-speed operation, or more in particular to a variable-ratio frequency divider adaptable for use with a timing generator of a test apparatus for conducting a high-precision timing test of an IC or LSI and the like.
2. Description of the Prior Art
One of the important component elements of an IC test apparatus is a timing generator. The timing generator has dual functions; one is to determine the timing (test period) of the test pattern applied to the IC to be tested, and the other is to specify the timing (the phase against the test period) at which an output signal of the IC impressed with the test pattern is compared with an expectation-value pattern. The timing signal generator for IC test roughly comprises a rate generator for determining a test period and a plurality of phase generators for generating a signal in a given phase against the test period. First, the prior art will be explained with reference to the drawings.
FIG. 1 is a block diagram showing an example of a conventional timing signal generator. For simplification, a single rate generator RG and a single phase generator PG are provided. In order to change the timing in real time, a test period signal 102 and a phase signal 103 are produced in response to a timing selection signal 101. The operation of this device will be explained briefly below.
In FIG. 1, upon application of the timing selection signal 101 to the circuit, it is introduced to a latch 7 in synchronism with a test period signal 102 that has thus far been produced. The latch 7 makes access to a rate memory 6 containing test period data and a phase memory 9 having phase signal data stored therein to read the test period data and the phase signal data, respectively.
In the rate generator RG, the test period signal 102 is generated by a rate counter for determining the test period which is an integral multiple of the basic clock period produced from an oscillator 1 and a variable delay circuit 3 for delaying the output of the rate counter 2 for improving the resolution of the test period more than the period of the basic clock.
The frequency-dividing ratio of the rate counter 2 and the delay time of the variable delay circuit 3 are controlled according to the data stored in the latch 4. In order to improve the resolution by the variable delay circuit 3, the data in the latch 4 is determined by an adder 5 for adding the delay time set in the preceding test period (the data stored in the latch 4) to a set value less than the period of the basic clock.
Further, in order to supply the basic clock in phase with the test period signal 102 to the phase generator PG for generating the phase signal 103, a phase clock 100 is generated by a variable delay circuit 8 for delaying the output of the oscillator 1.
The phase generator PG, on the other hand, produces a coincidence output at a time point when the phase data read out of the phase memory 9 and set in the latch 10 coincides with the count made by the phase counter 11, and further applies this coincidence output to a variable delay circuit 12 for producing the phase signal 103 in order to improve the phase resolution.
In the case where a preset counter is used as the rate counter for the variable-ratio frequency dividing operation, it is difficult to attain a high resolution of the clock after the frequency dividing process since the frequency of the basic clock is limited by the operating speed of the counter. For this reason, the basic clock is converted into a high frequency by inserting a prescaler before and after the preset counter thereby to attain a high resolution of the clock after frequency division. Since the minimum frequency divided is limited by the variable frequency dividing ratio of the prescalers, however, the range of the variable frequency ratio is small.
FIG. 2 is a circuit diagram showing an example of a conventional 2-modulus prescaler, and FIG. 3 is a block diagram showing an example of a variable-ratio frequency divider using the 2-modulus prescaler.
The prior art will be specifically explained with reference to FIGS. 2 and 3.
A prescaler 27 includes an OR gate 21, an AND gate 22, a NOR gate 23 and D flip-flops 24, 25, 26 for dividing the frequency of a basic clock f.sub.in and producing a frequency f.sub.out.
The number of frequency divisions is controlled by a selection signal SEL. For example, it is 5 when the selection signal SEL is "high", and 6 when the selection signal SEL is "low".
Counters 28, 29 are inserted as shown in FIG. 3 since it is impossible to make continuously variable frequency divisions only with the prescaler. In the case where the data value "A" and data value "B" are present in the counters 28 and 29 respectively, the number of frequency divisions is given by the equation (1) below. EQU N=f.sub.in /f.sub.out =6A+5(B-A)=A+5B (1)
This number of frequency divisions N can be changed in units of one by changing the value of data A, and in units of five by changing the value of data B. The minimum number of frequency divisions N which is continuously variable is 20 taking the condition B.gtoreq.A into consideration.
Generally, when the number of frequency divisions of the prescalers is U and L respectively, the relation U=L+1 is held, and therefore the minimum number of frequency divisions N.sub.min which is continuously variable is expressed by the equation (2) below. EQU N.sub.min =L(L-1) (2)
Specifically, if the number of frequency divisions U, L of the prescalers is increased in order to reduce the operating speed of the counter, the minimum number of frequency divisions N.sub.min is increased thereby to narrow the variable range of the number of frequency divisions N.
If an IC test is to be conducted at high operating speed on the one hand and various ICs are to be tested on the other hand, therefore, a variable-ratio frequency divider having a wide variable range of the number of frequency divisions is desired.